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| INTEGRATED CIRCUITS DATA SHEET TEF6892H Car radio integrated signal processor Product specification 2003 Oct 21 Philips Semiconductors Product specification Car radio integrated signal processor CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.7 7.7.1 7.7.2 8 9 10 11 11.1 11.1.1 11.1.2 11.1.3 FEATURES General I2C-bus Stereo decoder Noise blanking Weak signal processing RDS demodulator and decoder Tone/volume part GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Stereo decoder FM and AM noise blanker High cut control and de-emphasis Noise detector FM noise detector AM noise detector Multipath/weak signal processing Tone/volume control Input selector Loudness Volume/balance Treble Bass Fader/mute Beep generator and NAV input with output mixer RDS demodulator and decoder RDS demodulator RDS decoder LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS PROTOCOL Read mode Data byte 1; STATUS Data byte 2; LEVEL Data byte 3; USN and WAM 11.1.4 11.1.5 11.1.6 11.1.7 11.1.8 11.1.9 11.1.10 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 11.2.10 11.2.11 11.2.12 11.2.13 11.2.14 11.2.15 11.2.16 11.2.17 11.2.18 11.2.19 11.2.20 11.2.21 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 TEF6892H Data byte 4; RDS STATUS Data byte 5; RDS LDATM Data byte 6; RDS LDATL Data byte 7; RDS PDATM Data byte 8; RDS PDATL Data byte 9; RDS COUNT Data byte 10; RDS PBIN Write mode Subaddress 0H; RDS SET A Subaddress 1H; RDS SET B Subaddress 2H; RDSCLK Subaddress 3H; RDS CONTROL Subaddress 4H; CONTROL Subaddress 5H; CSALIGN Subaddress 6H; MULTIPATH Subaddress 7H; SNC Subaddress 8H; HIGHCUT Subaddress 9H; SOFTMUTE Subaddress AH; RADIO Subaddress BH; INPUT and ASI Subaddress CH; LOUDNESS Subaddress DH; VOLUME Subaddress EH; TREBLE Subaddress FH; BASS Subaddress 10H; FADER Subaddress 11H; BALANCE Subaddress 12H; MIX Subaddress 13H; BEEP Subaddress 1FH; AUTOGATE TEST AND APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2003 Oct 21 2 Philips Semiconductors Product specification Car radio integrated signal processor 1 1.1 FEATURES General TEF6892H * High integration * No external components except coupling capacitors for signal inputs and outputs * QFP44 package with small Printed-Circuit Board (PCB) footprint. 1.2 I2C-bus 1.5 Weak signal processing * Fast mode 400 kHz I2C-bus, interfaces to logic levels ranging from 2.5 to 5 V * Gated I2C-bus loop through to tuner IC - Eases PCB layout (crosstalk) - Allows mix of 400 kHz and 100 kHz busses - Low bus load reduces crosstalk - Buffered I/O circuit - Supply voltage shift between both buses allowed. * Shortgate function offers easy control with automatic gating of a single transmission; suited for TEA684x * Autogate function offers transparent microcontroller control with automatic on/off gating (programmable address). 1.3 Stereo decoder * FM weak signal processing with detectors for RF level, Ultrasonic Noise (USN) and Wideband AM (WAM) information * AM weak signal processing with detectors for level information * AM processing with soft mute and High Cut Control (HCC) * FM processing with soft mute, stereo blend and HCC * Setting of the sensitivity of the detectors and start and slope of the control functions via I2C-bus * Weather band de-emphasis * Level, USN and WAM read-out via I2C-bus (signal quality detectors) * Full support of tuner AF update functions with TEA684x tuner ICs, FM audio processing holds the detectors for the FM weak signal processing in their present state during RDS updating. 1.6 RDS demodulator and decoder * FM stereo decoder with high immunity to birdy noise and excellent pilot cancellation * Integrated IF roll-off correction controlled via I2C-bus * De-emphasis selectable between 75 and 50 s via I2C-bus. 1.4 Noise blanking * RDS/RBDS demodulator uses TEA684x reference frequency, no external crystal necessary * RDS/RBDS decoder with memory for two RDS data blocks provides block synchronization, error correction and flywheel function; block data and status information are available via the I2C-bus. * New fully integrated AM noise blanker with excellent performance * Fully integrated FM noise blanker with superior performance. 2003 Oct 21 3 Philips Semiconductors Product specification Car radio integrated signal processor 1.7 Tone/volume part 2 GENERAL DESCRIPTION TEF6892H * Input selector for four inputs: - Two external stereo inputs (CD and TAPE) - One mono input (PHONE) - One internal stereo input (AM or FM). * Integrated tone control and audio filters without external components * Volume control from +20 to -79 dB in 1 dB steps; programmable 20 dB loudness control included * Programmable loudness control with bass boost or as bass and treble boost * Treble control from -14 to +14 dB in 2 dB steps * Bass control from -14 to +14 dB in 2 dB steps with selectable characteristics * Good undistorted performance for any step size, including mute * Audio Step Interpolation (ASI) available for the following audio controls: - Mute - Loudness - Volume/balance - Bass - Fader. * ASI also realizes Alternative Frequency (AF) mute for inaudible RDS update * Integrated beep generator * Navigation (NAV) input * Output mixer circuit for beep or NAV signal at output stages. 3 ORDERING INFORMATION TYPE NUMBER TEF6892H The TEF6892H is a monolithic BiMOS integrated circuit comprising the stereo decoder function, weak signal processing and ignition noise blanking facility for AM and FM combined with input selector and tone/volume control for AM and FM car radio applications. The RDS/RBDS demodulator function and the RDS/RBDS decoder function are included. The device operates with a supply voltage of 8 to 9 V. PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2 2003 Oct 21 4 Philips Semiconductors Product specification Car radio integrated signal processor 4 QUICK REFERENCE DATA SYMBOL VCC ICC PARAMETER supply voltage supply current normal mode standby RDS; audio on standby audio; RDS on standby Stereo decoder path cs S/N THD channel separation signal-to-noise ratio total harmonic distortion fFMMPX = 1 kHz fFMMPX = 20 Hz to 15 kHz FM mode; fFMMPX = 1 kHz THD = 0.1%; Gvol = -6 dB 40 75 - 2 CONDITIONS TEF6892H MIN. TYP. MAX. UNIT 8.0 - - - - 8.5 28 24 19 15 - - - - 9.0 - - - - - - 0.3 - V mA mA mA mA dB dB % Tone/volume control Vi(max)(rms) maximum input voltage level at pins TAPEL, TAPER, CDL, CDR, CDCM, PHONE and PHCM (RMS value) V Vi(NAV)(max)(rms) maximum input voltage level at pin NAV (RMS value) THD total harmonic distortion THD = 1%; fNAV = 1 kHz TAPE and CD inputs; faudio = 20 Hz to 20 kHz; Vi = 1 V (RMS) maximum setting minimum setting 0.3 - - - V % 0.01 0.1 Gvol Gstep(vol) Gloudness volume/balance gain control step resolution gain (volume) loudness gain control - - - 20 -59 1 0 -20 14 -14 2 14 -14 2 - - - - - - - - - - - dB dB dB dB dB dB dB dB dB dB dB floudness(low) = 50 Hz; high boost on maximum setting; 1 kHz tone minimum setting; 1 kHz tone - - - - - maximum setting; symmetrical boost - minimum setting; asymmetrical cut - - Gtreble Gstep(treble) Gbass Gstep(bass) treble gain control step resolution gain (treble) bass gain control step resolution gain (bass) maximum setting minimum setting 2003 Oct 21 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Oct 21 6 5 Philips Semiconductors Car radio integrated signal processor BLOCK DIAGRAM input select 22 20 21 24 23 25 26 + + - + INPUT + SELECT + - + + 0 to -20 dB low f: 50/100 Hz high boost vol: +20 to -59 dB bal: L/R, 0 to -79 dB mute +14 to -14 dB f: 8 to 15 kHz +14 to -14 dB f: 60 to 120 Hz shelve/band-pass front/rear 0 to -59 dB mute: LF, RF, LR, RR mix: LF, RF, LR, RR 27 CDL CDR CDCM TAPEL TAPER PHONE PHCM LOUDNESS asi VOLUME/ BALANCE/ MUTE asi amfmsoftmute afumute TREBLE BASS asi FRONT/ REAR FADER asi 28 MUTE asi level/off pitch BEEP on/off 32 MIX 29 30 LFOUT RFOUT LROUT RROUT AUDIO STEP INTERPOLATION (asi) NAV asi time asi active roll-off correction MPX FMMPX 5 PILOT CANCEL 19 kHz level fref AM 7 PILOT/ REFERENCE PLL stereo adjust fm/am f: 1.5 to 15 kHz/wide 50/75 s STEREO DECODER 38 kHz fmsnc stereo 57 kHz Iref NOISE BLANKER HIGH CUT DE-EMPHASIS amnb fmnb amfmhcc standby SUPPLY Vref 16 17 18 41 44 NOISE DETECT nb sensitivity NOISE DETECT detection timings and control PULSE TIMER amnb addr I2C-BUS INTERFACE read fmnb write autogate VCC AGND CREF DGND ADDR USN 6 MPXRDS TEF6892H 43 42 DETECT 1 LEVEL DETECT SCLG SDAG 3 4 sclg sdag WAM DETECT level PULSE TIMER SCL SDA snc start, slope hcc start, slope sm start, slope sclg SNC HCC SM fmsnc amfmhcc amfmsoftmute sdag usn usn sensitivity wam wam sensitivity MULTIPATH/ WEAK SIGNAL DETECTION AND LOGIC reset/hold AFSAMP AFHOLD FREF 11 fref 8, 12, 13, 14, 15, 19, 31, 33, 34, 35, 36, 40 i.c. 10 9 hold afus handbook, full pagewidth mode RDS 57 kHz RDS DEMODULATOR rds 39 RDCL 38 37 2 afumute RDS DECODER Product specification RDDA TEF6892H RDQ RDSGND MHC356 Fig.1 Block diagram. Philips Semiconductors Product specification Car radio integrated signal processor 6 PINNING SYMBOL LEVEL RDSGND SCLG SDAG FMMPX MPXRDS AM i.c. AFHOLD AFSAMP FREF i.c. i.c. i.c. i.c. VCC AGND CREF i.c. CDR CDCM CDL TAPER TAPEL PHONE PHCM LFOUT RFOUT LROUT RROUT i.c. NAV i.c. i.c. i.c. i.c. RDQ RDDA RDCL i.c. 2003 Oct 21 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 level detector input RDS ground gated I2C-bus clock port gated I2C-bus data port FM-MPX input for audio processing DESCRIPTION TEF6892H FM-MPX input for weak signal processing, noise blanker and RDS demodulator AM audio input internally connected FM weak signal processing hold input trigger signal input for quality measurement reference frequency input 75.4 kHz internally connected internally connected internally connected internally connected supply voltage analog ground reference voltage capacitor internally connected CD right input CD common input CD left input tape right input tape left input phone input phone common input left front output right front output left rear output right rear output internally connected audio input for navigation voice signal internally connected internally connected internally connected internally connected RDS/RBDS demodulator quality information output RDS/RBDS decoder data available or RDS/RBDS demodulator data output RDS/RBDS demodulator clock input or output internally connected 7 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL DGND SDA SCL ADDR PIN 41 42 43 44 digital ground I2C-bus data input or output I2C-bus clock input address select input DESCRIPTION 41 DGND 38 RDDA 44 ADDR 39 RDCL 37 RDQ 42 SDA 43 SCL 40 i.c. 36 i.c. 35 i.c. handbook, full pagewidth LEVEL RDSGND SCLG SDAG FMMPX MPXRDS AM i.c. AFHOLD 1 2 3 4 5 6 7 8 9 34 i.c. 33 i.c. 32 NAV 31 i.c. 30 RROUT 29 LROUT TEF6892H 28 RFOUT 27 LFOUT 26 PHCM 25 PHONE 24 TAPEL 23 TAPER AFSAMP 10 FREF 11 i.c. 12 i.c. 13 i.c. 14 i.c. 15 VCC 16 AGND 17 CREF 18 i.c. 19 CDR 20 CDCM 21 CDL 22 MHC354 Fig.2 Pin configuration. 7 7.1 FUNCTIONAL DESCRIPTION Stereo decoder settings to compensate different frequency responses of the tuner part. The MPX signal is decoded in the stereo decoder part. A PLL is used for the regeneration of the 38 kHz subcarrier. The fully integrated oscillator is adjusted by a digital auxiliary PLL into the capture range of the main PLL. The auxiliary PLL needs an external reference frequency (75.4 kHz) which is provided by the tuner ICs of the NICE family (TEA684x). The required 19 and 38 kHz signals are generated by division of the oscillator output signal in a logic circuit. The 19 kHz quadrature phase signal is fed to the 19 kHz phase detector, where it is compared with the incoming pilot tone. The DC output signal of the phase detector controls the oscillator (PLL). The FMMPX input is the input for the MPX signal from the tuner. The input gain can be selected in three settings to match the input to the RF front-end circuit. A fourth setting is used for weather band mode, which may require a gain of 23.5 dB. A low-pass filter provides the necessary signal delay for FM noise blanking and suppression of high frequency interferences into the stereo decoder input. The output signal of this filter is fed to the roll-off correction circuit. This circuit compensates the frequency response caused by the low-pass characteristic of the tuner circuit with its IF filters. The roll-off correction circuit is adjustable in four 2003 Oct 21 8 Philips Semiconductors Product specification Car radio integrated signal processor The pilot detector is driven by an internally generated in-phase 19 kHz signal. Its pilot dependent voltage activates the stereo indicator bit and sets the stereo decoder to stereo mode. The same voltage is used to control the amplitude of an anti-phase internally generated 19 kHz signal. In the pilot canceller, the pilot tone is compensated by this anti-phase 19 kHz signal. The signal is then decoded in the decoder part. The side signal is demodulated and combined with the main signal to the left and right audio channels. A fine adjustment of the roll-off compensation is done by adjusting the gain of the L-R signal in 16 steps. A smooth mono to stereo takeover is achieved by controlling the efficiency of the matrix by the FMSNC signal from the weak signal processing block. 7.2 FM and AM noise blanker TEF6892H MPXRDS signal can be adjusted in four steps, the triggering from the LEVEL signal in three steps. 7.4.2 AM NOISE DETECTOR The trigger pulse for the AM noise blanker is derived from the AM audio signal. The noise spikes are detected by a slew rate detector, which detects excessive slew rates which do not occur in normal audio signals. The sensitivity of the AM noise blanker can be adjusted in four steps. 7.5 Multipath/weak signal processing The multipath (MPH)/weak signal processing block detects quality degradations in the incoming FM signal and controls the processing of the audio signal accordingly. There are three different quality criteria: * The average value of the level voltage * The AM components on the level voltage [Wideband AM (WAM)] * The high frequency components in the MPX signal [Ultrasonic Noise (USN)]. The level voltage is converted to a digital value by an 8-bit analog-to-digital converter. A digital filter circuit (WAM filter) derives the wideband AM components from the level signal. The high frequency components in the MPX signals are measured with an analog-to-digital converter (USN ADC) at the output of the 100 kHz high-pass filter in the MPXRDS path. The values of these three signals are externally available via the I2C-bus. In the weak signal processing block the three digital signals are combined in a specific way and used for the generation of control signals for soft mute, stereo blend (stereo noise control, FMSNC) and high cut control (AMFMHCC). The sensitivities of the detector circuits (WAM and USN) are adjustable via the I2C-bus. Also the start values and the slopes of the control functions soft mute, stereo blend and high cut control can be set via the I2C-bus. Soft mute, stereo blend and HCC are set on hold during the AF updating (quality check of alternative frequency) to avoid an influence of the tuning procedure on the weak signal processing conditions. In AM mode the soft mute and high cut control are available too, the weak signal block is controlled by the average value of the level voltage. The FM/AM switch selects the output signal of the stereo decoder (FM mode) or the signal from the AM input for the noise blanker block. In FM mode the noise blanker operates as a sample and hold circuit, while in AM mode it mutes the audio signal during the interference pulse. The blanking pulse which triggers the noise blanker is generated in the noise detector block. 7.3 High cut control and de-emphasis The High Cut Control (HCC) part is a low-pass filter circuit with eight different static roll-off response curves. The cut-off frequencies of these filter curves can be selected by I2C-bus to match different application requirements. The HCC circuit also provides a dynamic control of the filter response. This function is controlled by the AMFMHCC signal from the weak signal processing. The signal passes the de-emphasis block with two de-emphasis values (50 and 75 s), which can be selected via I2C-bus, and is fed to the input selector. 7.4 7.4.1 Noise detector FM NOISE DETECTOR The trigger signal for the FM noise detector is derived from the MPXRDS input signal and the LEVEL signal. In the MPXRDS path a four pole high-pass filter (100 kHz) separates the noise spikes from the wanted MPX signal. Another detector circuit triggers on noise spikes on the level voltage. The signals of both detectors are combined to achieve a reliable trigger signal for the noise blanker. AGC circuits in the detector part control the gain depending on the average noise in the signals to prevent false triggering. The sensitivity of the triggering from the 2003 Oct 21 9 Philips Semiconductors Product specification Car radio integrated signal processor 7.6 Tone/volume control 7.6.5 BASS TEF6892H The tone/volume control part consists of the following stages: * Input selector * Loudness control * Volume/balance control with muting * Treble control * Bass control * Fader and output mute * Beep generator * NAV input * Output mixer. The settings of all stages are controlled via the I2C-bus. The stages input selector, loudness, volume/balance, bass, and fader/output mute include the Audio Step Interpolation (ASI) function. This minimizes pops by smoothing the transitions in the audio signal during the switching of the controls. The transition time of the ASI function is programmable by I2C-bus in four steps. 7.6.1 INPUT SELECTOR The characteristic of the bass attenuation curves can be set to shelve or band-pass. Four different frequencies can be selected as centre frequency of the band-pass curve. Figures 21 and 22 show the bass curves with a band-pass filter frequency of 60 Hz. The control range is between +14 and -14 dB in steps of 2 dB. 7.6.6 FADER/MUTE The four fader/mute blocks are located at the end of the tone/volume chain. The control range of these attenuators is 0 to -59 dB. The step size is: * 1 dB between 0 and -15 dB * 2.5 dB between -15 and -45 dB * 3 dB between -45 and -51 dB * 4 dB between -51 and -59 dB. 7.6.7 BEEP GENERATOR AND NAV INPUT WITH OUTPUT MIXER The output mixer circuit can add an additional audio signal to any of the four outputs together with the main signal or instead of the main signal. The additional signal can be generated internally by the beep generator with four different audio frequencies or applied to the NAV input, for instance a navigation voice signal. 7.7 7.7.1 RDS demodulator and decoder RDS DEMODULATOR The input selector selects one of four input sources: * Two external stereo inputs (CD and TAPE) * One external mono input (PHONE) * One internal stereo input (AM/FM). 7.6.2 LOUDNESS The output of the input selector is fed into the loudness circuit. Four different loudness curves can be selected via the I2C-bus. The control range is between 0 and -20 dB with a step size of 1 dB; see Figs 16 to 19. 7.6.3 VOLUME/BALANCE The volume/balance control is used for volume setting and also for balance adjustment. The control range of the volume/balance control is between +20 and -59 dB in steps of 1 dB. The combination of loudness and volume/balance realizes an overall control range of +20 to -79 dB. 7.6.4 TREBLE The RDS demodulator recovers and regenerates the continuously transmitted RDS or RBDS data stream of the multiplex signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) and quality (RDQ) for external use or further processing by the integrated RDS decoder. The RDS demodulator uses the reference frequency (75.4 kHz) from the tuner IC and does not need a crystal. 7.7.2 RDS DECODER The signal is then fed to the treble control stage. The control range is between +14 and -14 dB in steps of 2 dB. Figure 20 shows the control characteristic. Four different filter frequencies can be selected. 2003 Oct 21 10 The RDS decoder provides block synchronization, error correction and flywheel function for reliable extraction of RDS or RBDS block data. Different modes of operation can be selected to fit different application requirements. Availability of new data is signalled by read bit RDAV and output pin RDDA. Up to two blocks of data and status information are available via the I2C-bus in a single transmission. Philips Semiconductors Product specification Car radio integrated signal processor 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC Vi Tstg Tamb Vesd supply voltage input voltage for any pin storage temperature ambient temperature electrostatic discharge voltage note 1 note 2 Notes 1. Machine model (R = 0 , C = 200 pF). 2. Human body model (R = 1.5 k, C = 100 pF). 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS PARAMETER CONDITIONS MIN. -0.3 -0.3 -65 -40 -200 -2000 TEF6892H MAX. +10 +150 +85 +200 +2000 V VCC + 0.3 V UNIT C C V V VALUE 61 UNIT K/W thermal resistance from junction to ambient in free air 10 CHARACTERISTICS FM part: fFMMPX = 1 kHz at VFMMPX = 767 mV (RMS); pilot off (100% FM). AM part: fAM = 1 kHz at VAM = 967 mV (RMS) (100% AM). Treble: 10 kHz filter frequency. Bass: 60 Hz filter frequency. Loudness: 50 Hz filter frequency; treble loudness on. VCC = 8.5 V; Tamb = 25 C; see Fig.23; unless otherwise specified. SYMBOL VCC ICC PARAMETER supply voltage supply current normal mode standby RDS; audio on standby audio; RDS on standby Logic pins VIH HIGH-level input voltage pins SDA, SCL, ADDR, SDAG and RDCL pins AFHOLD and AFSAMP VIL LOW-level input voltage pins SDA, SCL, ADDR, SDAG and RDCL pins AFHOLD and AFSAMP VOH VOL HIGH-level output voltage pins RDCL and RDDA; IOH = 2.5 A LOW-level output voltage pins SCLG, RDCL and RDDA; IOL = 3 mA; note 1 pin SDA; IOL = 3 mA 1.75 1.75 -0.2 -0.2 2.6 - - - - - - - - - 5.5 5.5 +1.0 +1.0 - 0.4 0.4 V V V V V V V CONDITIONS MIN. 8.0 - - - - TYP. 8.5 28 24 19 15 MAX. 9.0 - - - - UNIT V mA mA mA mA 2003 Oct 21 11 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Stereo decoder and AM path Vo(FM)(rms) FM mono output voltage (RMS value) on pins LFOUT and RFOUT AM output voltage (RMS value) on pins LFOUT and RFOUT input gain on pins FMMPX, MPXRDS and AM fFMMPX = 1 kHz; 91% FM modulation 750 without pilot (VFMMPX = 698 mV) fAM = 1 kHz; VAM = 870 mV; 90% AM modulation see Table 61 ING[1:0] = 00; all inputs ING[1:0] = 01; all inputs ING[1:0] = 10; all inputs ING[1:0] = 11; FMMPX ING[1:0] = 11; MPXRDS and AM cs gc(L-R) channel separation roll-off correction for coarse adjustment of separation fFMMPX = 1 kHz see Table 45; measure 1 kHz level for L - R modulation; compare to 1 kHz level for L + R modulation CSR[1:0] = 00 CSR[1:0] = 01 CSR[1:0] = 10 CSR[1:0] = 11 gf(L-R) stereo adjust for fine adjustment of separation see Table 46; measure 1 kHz level for L - R modulation; compare to 1 kHz level for L + R modulation CSA[3:0] = 0000 CSA[3:0] = 0001 : CSA[3:0] = 1110 CSA[3:0] = 1111 S/N signal-to-noise ratio fFMMPX = 20 Hz to 15 kHz; referenced to 1 kHz at 91% FM modulation; DEMP = 1 (de-em = 50 s) FM mode fFMMPX = 1 kHz VFMMPX = 50%; L; pilot on VFMMPX = 50%; R; pilot on Vo(bal) mono channel balance V oL --------V oR pilot signal suppression FM mode - - - -1 - - - - 0.3 0.3 0.3 +1 % % % dB - - - - - 75 0 0.2 : 2.8 3.0 - - - - - - - dB dB dB dB dB dB - - - - 0 0.4 0.8 1.2 - - - - dB dB dB dB - - - - - 40 0 3 6 23.5 0 - - - - - - - dB dB dB dB dB dB 800 950 1200 mV Vo(AM)(rms) 1080 1360 mV Gi THD total harmonic distortion 19 9% pilot; fpilot = 19 kHz; referenced to 1 kHz at 91% FM modulation; DEMP = 1 (de-em = 50 s) 12 40 50 - dB 2003 Oct 21 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL PARAMETER subcarrier suppression CONDITIONS modulation off; referenced to 1 kHz at 91% FM modulation fsc = 38 kHz fsc = 57 kHz fsc = 76 kHz MIN. TYP. MAX. UNIT 35 40 50 24 50 - 60 - - - - - dB dB dB dB PSRR Vout power supply ripple rejection frequency response FM mode; fripple = 100 Hz; VCC(AC) = Vripple = 100 mV (RMS) FM mode fFMMPX = 20 Hz fFMMPX = 15 kHz -0.5 -0.5 - - - 1.3 - - - - 3.18 2.12 4.0 2.7 2 - +0.5 +0.5 - - 5.5 - - 30 dB dB kHz kHz % % dB mV fcut-off(de-em) cut-off frequency of de-emphasis filter -3 dB point; see Fig.15 DEMP = 1 (de-em = 50 s) DEMP = 0 (de-em = 75 s) mi(pilot)(rms) pilot threshold modulation stereo for automatic switching by on pilot input voltage off (RMS value) hysteresis of pilot threshold voltage minimum reference input voltage reference frequency for stereo PLL and RDS demodulator hyspilot Vref(min) fref 75361 75368 75375 Hz Noise blanker FM PART tsup(min) VMPXRDS(M) minimum suppression time noise blanker sensitivity at MPXRDS input (peak value of noise pulses) see Table 62; tpulse = 10 s; fpulse = 300 Hz NBS[1:0] = 00 NBS[1:0] = 01 NBS[1:0] = 10 NBS[1:0] = 11 VLEVEL(M) noise blanker sensitivity at LEVEL input (peak value of noise pulses) see Table 65; tpulse = 10 s; fpulse = 300 Hz NBL[1:0] = 00 NBL[1:0] = 01 NBL[1:0] = 10 - - - 9 18 28 - - - mV mV mV - - - - 90 150 210 270 - - - - mV mV mV mV - 15 - s 2003 Oct 21 13 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL AM PART tsup(min) MAM PARAMETER CONDITIONS MIN. - TYP. MAX. - UNIT s minimum suppression time noise blanker sensitivity see Table 62; faudio = 2 kHz NBS[1:0] = 00 NBS[1:0] = 01 NBS[1:0] = 10 NBS[1:0] = 11 200 - - - - 110 140 175 220 - - - - % % % % Weak signal processing DETECTORS Veq(USN) USN sensitivity equivalent see Fig.5; fMPXRDS = 150 kHz; level voltage VMPXRDS = 250 mV (RMS); HCMP = 1; note 2 USS[1:0] = 00 USS[1:0] = 01 USS[1:0] = 10 USS[1:0] = 11 Veq(WAM) WAM sensitivity equivalent level voltage see Fig.6; VLEVEL = 200 mV (p-p) at f = 21 kHz on the level voltage; HCMP = 1; note 2 WAS[1:0] = 00 WAS[1:0] = 01 WAS[1:0] = 10 WAS[1:0] = 11 tLEVEL(attack) level detector attack time (soft mute and HCC) see Table 49; LETF = 0; SEAR = 0 LET[1:0] = 00 LET[1:0] = 01 LET[1:0] = 10 LET[1:0] = 11 see Table 49; LETF = 1; SEAR = 0 LET[1:0] = 00 LET[1:0] = 01 LET[1:0] = 10 LET[1:0] = 11 search mode; SEAR = 1 - - - - - 0.5 0.17 0.06 0.06 60 - - - - - s s s s ms - - - - 3 3 1.5 0.5 - - - - s s s s - - - - 2.5 2 1.5 0.5 - - - - V V V V - - - - 2.5 2 1.5 0.5 - - - - V V V V 2003 Oct 21 14 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL tLEVEL(decay) PARAMETER level detector decay time (soft mute and HCC) CONDITIONS see Table 49; LETF = 0; SEAR = 0 LET[1:0] = 00 LET[1:0] = 01 LET[1:0] = 10 LET[1:0] = 11 see Table 49; LETF = 1; SEAR = 0 LET[1:0] = 00 LET[1:0] = 01 LET[1:0] = 10 LET[1:0] = 11 search mode; SEAR = 1 MIN. - - - - - - - - - - - - - - - - - - - - - 3 6 TYP. MAX. - - - - - - - - - - - - - - - - - - - - - UNIT s s s s s s s s ms s s s s ms s s s s ms ms ms 1.5 1.5 0.5 0.5 0.17 0.06 60 0.5 0.5 0.5 0.25 60 12 24 6 6 60 1 1 tMPH(attack) multipath detector attack time (SNC) see Table 50; SEAR = 0 MPT[1:0] = 00 MPT[1:0] = 01 MPT[1:0] = 10 MPT[1:0] = 11 search mode; SEAR = 1 tMPH(decay) multipath detector decay time (SNC) see Table 50; SEAR = 0 MPT[1:0] = 00 MPT[1:0] = 01 MPT[1:0] = 10 MPT[1:0] = 11 search mode; SEAR = 1 tUSN(attack) tUSN(decay) USS USN detector attack time (soft mute and SNC) USN detector decay time (soft mute and SNC) USN detector desensitization USN sensitivity setting (USS) versus level voltage (USN sensitivity setting is automatically reduced as level voltage decreases) VLEVEL > 1.25 V 1.25 V > VLEVEL > 1.125 V 1.125 V > VLEVEL > 1.0 V 1.0 V > VLEVEL - - - - - - - - - - - 1 1 1 3 2 1 0 - - - - - - - ms ms ms tWAM(attack) tWAM(decay) tpeak(USN)(attack) WAM detector attack time (SNC) WAM detector decay time (SNC) peak detector for USN attack time for read-out via I2C-bus 2003 Oct 21 15 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL tpeak(USN)(decay) PARAMETER peak detector for USN decay time for read-out via I2C-bus CONDITIONS MIN. - TYP. 10 MAX. - UNIT ms tpeak(WAM)(attack) peak detector for WAM attack time for read-out via I2C-bus tpeak(WAM)(decay) peak detector for WAM decay time for read-out via I2C-bus CONTROL FUNCTIONS Vstart(mute) soft mute start voltage see Fig.12; voltage at pin LEVEL that causes mute = 3 dB; MSL[1:0] = 11 MST[2:0] = 000 MST[2:0] = 001 MST[2:0] = 010 MST[2:0] = 011 MST[2:0] = 100 MST[2:0] = 101 MST[2:0] = 110 MST[2:0] = 111 Cmute soft mute slope mute C mute = ---------------V eq see Fig.13; slope of soft mute attenuation with respect to level voltage; MST[2:0] = 000 MSL[1:0] = 00 MSL[1:0] = 01 MSL[1:0] = 10 MSL[1:0] = 11 mute(max) maximum soft mute attenuation by USN see Fig.14; fMPXRDS = 150 kHz; VMPXRDS = 0.6 V (RMS); USS[1:0] = 11 UMD[1:0] = 00 UMD[1:0] = 01 UMD[1:0] = 10 UMD[1:0] = 11 Vstart(SNC) SNC stereo blend start voltage see Fig.7; voltage at pin LEVEL that causes channel separation = 10 dB; SSL[1:0] = 10 SST[3:0] = 0000 : SST[3:0] = 1000 : SST[3:0] = 1111 - 1 - ms - 10 - ms - - - - - - - - 0.75 0.88 1 1.12 1.25 1.5 1.75 2 - - - - - - - - V V V V V V V V - - - - 8 16 24 32 - - - - dB/V dB/V dB/V dB/V - - - - 3 6 9 12 - - - - dB dB dB dB - - - - - 1.5 : 2.0 : 2.45 - - - - - V V V V V 2003 Oct 21 16 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL CSNC PARAMETER SNC slope cs C SNC = -----------V eq CONDITIONS see Fig.8; slope of channel separation between 30 dB and 10 dB with respect to level voltage; SST[3:0] = 1010 SSL[1:0] = 00 SSL[1:0] = 01 SSL[1:0] = 10 SSL[1:0] = 11 MIN. TYP. MAX. UNIT - - - - 38 51 63 72 - - - - dB/V dB/V dB/V dB/V Vstart(HCC) HCC start voltage see Fig.9; faudio = 10 kHz; voltage at pin LEVEL that causes HCC = 3 dB; HSL[1:0] = 10 HST[2:0] = 000 HST[2:0] = 001 HST[2:0] = 010 HST[2:0] = 011 HST[2:0] = 100 HST[2:0] = 101 HST[2:0] = 110 HST[2:0] = 111 - - - - - - - - 1.17 1.42 1.67 1.92 2.17 2.67 3.17 3.67 - - - - - - - - V V V V V V V V CHCC HCC slope HCC C HCC = ---------------V eq see Fig.10; faudio = 10 kHz; HST[2:0] = 010 HSL[1:0] = 00 HSL[1:0] = 01 HSL[1:0] = 10 HSL[1:0] = 11 - - - - - - 9 11 14 18 10 14 - - - - - - dB/V dB/V dB/V dB/V dB dB HCC(max) maximum HCC attenuation see Fig.10; faudio = 10 kHz HCSF = 1 HCSF = 0 see Table 56; -3 dB point (first order filter) HCF[2:0] = 000 HCF[2:0] = 001 HCF[2:0] = 010 HCF[2:0] = 011 HCF[2:0] = 100 HCF[2:0] = 101 HCF[2:0] = 110 HCF[2:0] = 111 - - - - - - - - 1.5 2.2 3.3 4.7 6.8 10 wide - - - - - - - kHz kHz kHz kHz kHz kHz - - fcut-off cut-off frequency of fixed HCC unlimited - Analog-to-digital converters for I2C-bus LEVEL ANALOG-TO-DIGITAL CONVERTER (8-BIT); see Fig.4 VLEVEL(min) lower voltage limit of conversion range 17 - 0.25 - V 2003 Oct 21 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL VLEVEL(max) VLEVEL VUSN(min)(rms) VUSN(max)(rms) VUSN(rms) PARAMETER upper voltage limit of conversion range bit resolution voltage CONDITIONS MIN. - - TYP. 4.25 15.7 MAX. - - - - - UNIT V mV ULTRASONIC NOISE ANALOG-TO-DIGITAL CONVERTER (4-BIT); see Fig.5 conversion range lower voltage limit (RMS value) conversion range upper voltage limit (RMS value) bit resolution voltage (RMS value) fFMMPX = 150 kHz fFMMPX = 150 kHz - - - 0 0.75 50 V V mV WIDEBAND AM ANALOG-TO-DIGITAL CONVERTER (4-BIT); see Fig.6 VWAM(min)(p-p) lower voltage limit of conversion range (peak-to-peak value) upper voltage limit of conversion range (peak-to-peak value) bit resolution voltage (peak-to-peak value) fLEVEL = 21 kHz - 0 - mV VWAM(max)(p-p) fLEVEL = 21 kHz - 800 - mV VWAM(p-p) - 53.3 - mV Tone/volume control Zi input impedance at pins TAPEL, TAPER, CDL and CDR input impedance at pin PHONE Zo output impedance at pins LFOUT, RFOUT, LROUT and RROUT signal gain from main source input to LFOUT, RFOUT, LROUT and RROUT outputs signal gain from NAV input to LFOUT, RFOUT, LROUT and RROUT outputs maximum input voltage level at pins TAPEL, TAPER, CDL, CDR and PHONE (RMS value) THD = 0.1%; Gvol = -6 dB 80 - - k 50 - - - - 100 k Gs(main) -1 - +1 dB Gs(NAV) -1.5 0 +1.5 dB Vi(max)(rms) 2 - - V Vi(NAV)(max)(rms) maximum input voltage level at pin NAV (RMS value) THD = 1% 0.3 - - V 2003 Oct 21 18 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL Vo(max)(rms) PARAMETER maximum output voltage (RMS value) frequency response (pins TAPER, TAPEL, CDR and CDL) common mode rejection ratio CONDITIONS THD = 0.1%; Gvol = +6 dB worst case load: RL = 2 k, CL = 10 nF, THD = 1% upper -0.5 dB point; referenced to 1 kHz faudio = 20 Hz to 20 kHz on CD and PHONE inputs Gvol = 0 dB Gvol = -15 dB MIN. 2 2 20 - - - TYP. MAX. - - - UNIT V V kHz fmax CMRR 40 55 60 90 75 70 - - - - - 80 105 90 - 0.01 0.02 0.02 0.05 0.01 - - - - - - - 0.1 0.1 0.2 0.2 0.2 1 dB dB dB dB dB dB % % % % % % cs S channel separation input isolation of one selected source to any other input total harmonic distortion faudio = 20 Hz to 20 kHz faudio = 1 kHz faudio = 20 Hz to 10 kHz faudio = 20 kHz TAPE and CD inputs faudio = 20 Hz to 10 kHz; Vi = 1 V (RMS) faudio = 1 kHz; Vi = 2 V (RMS); Gvol = 0 dB faudio = 20 Hz to 10 kHz; Vi = 2 V (RMS); Gvol = -10 dB THD faudio = 25 Hz; Vi = 500 mV (RMS); - Gbass = +8 dB; Gvol = 0 dB faudio = 4 kHz; Vi = 500 mV (RMS); - Gtreble = +8 dB; Gvol = 0 dB NAV input; faudio = 1 kHz; Vo = 300 mV (RMS) Vnoise(rms) noise voltage (RMS value) CCIR-ARM weighted and 20 kHz `brick wall' without input signal and shorted AF inputs Gvol = 0 dB Gbass = +6 dB; Gtreble = +6 dB; Gvol = 0 dB Gvol = 20 dB; TAPE input (stereo) Gvol = 20 dB; CD input (quasi-differential) Gvol = -10 dB Gvol = -40 dB; Gloudness = -20 dB outputs muted using `A-weighting' filter and 20 kHz `brick wall'; Gvol = -10 dB; Gloudness = -10 dB NAV input - - - - - - - - - 12 24 71 100 10 9.5 5 6.8 20 35 100 140 18 13.5 12 10 V V V V V V V V - 16 40 V 2003 Oct 21 19 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL Gstep PARAMETER step error (all controls) between all adjoining steps, all outputs ASI time constant (switching time from any setting to any other setting) CONDITIONS G = +20 to -36 dB G = -36 to -59 dB see Table 67 AST[1:0] = 00 AST[1:0] = 01 AST[1:0] = 10 AST[1:0] = 11 MIN. - - - - TYP. MAX. 0.5 1.0 UNIT dB dB TCASI - - - - - 1 3 10 30 7 - - - - - ms ms ms ms mV Voffset(max) maximum DC offset between any two settings (non-consecutive) on any one audio control or any one dynamic weak signal processing control VCC(AC) = Vripple = 200 mV (RMS) fripple = 20 to 100 Hz fripple = 1 kHz fripple = 1 to 20 kHz PSRR power supply ripple rejection 35 50 50 - - 46 75 65 110 100 - - - - - dB dB dB dB ms ct tturn-on crosstalk between bus inputs and signal outputs turn-on time from VCC applied to 66% final DC voltage at outputs fclk = 100 kHz; note 3 LOUDNESS floudness(low) loudness low boost frequency; without influence of coupling capacitors loudness filter response; without influence of coupling capacitors loudness gain control amplitude decrease = -3 dB LLF = 0 LLF = 1 amplitude decrease = -1 dB; frequency referred to 100 kHz; high boost on floudness(low) = 50 Hz; high boost on; see Fig.16 maximum setting; 1 kHz tone minimum setting; 1 kHz tone minimum setting; 50 Hz tone minimum setting; 10 kHz tone minimum setting; 100 kHz tone step size; 1 kHz tone VOLUME Gvol volume/balance gain control see Table 73 maximum setting minimum setting - - 20 -59 -80 - - -70 dB dB dB - - - - - - 0 -20 -3 -16 -15 1 - - - - - - dB dB dB dB dB dB - - - 50 100 10 - - - Hz Hz kHz floudness(high) Gloudness mute attenuation; 20 Hz to 20 kHz - input 2003 Oct 21 20 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL Gstep(vol) Gset Gtrack TREBLE fcut-off(treble) PARAMETER step resolution gain (volume) gain set error gain tracking error between left and right CONDITIONS see Table 73 Gvol = +20 to -36 dB Gvol = -36 to -59 dB Gvol = +20 to -36 dB Gvol = -36 to -59 dB see Table 77; -3 dB frequency referred to 100 kHz TRF[1:0] = 00 TRF[1:0] = 01 TRF[1:0] = 10 TRF[1:0] = 11 MIN. - -1 -3 - - 1 0 0 0 0 TYP. MAX. - +1 +3 1 3 UNIT dB dB dB dB dB treble control filter cut-off frequency - - - - - - - 8 10 12 15 14 -14 2 - - - - - - - kHz kHz kHz kHz dB dB dB Gtreble treble gain control see Table 76 maximum setting minimum setting Gstep(treble) BASS fc(bass) step resolution gain (treble) see Table 76 bass control filter centre frequency see Table 81 BAF[1:0] = 00 BAF[1:0] = 01 BAF[1:0] = 10 BAF[1:0] = 11 - - - - - - 60 80 100 120 1.0 1.8 - - - - - - Hz Hz Hz Hz - dB Qbass EQbow bass filter quality factor equalizer bowing Gbass = +12 dB faudio = 1 kHz; Vi = 500 mV (RMS); Gbass = +12 dB; fc(bass) = 60 Hz; Gtreble = +12 dB; fcut-off(treble) = 10 kHz; see Fig.3 see Table 80 maximum setting; symmetrical boost minimum setting; symmetrical cut Gbass bass gain control - 14 -14 -14 2 - - - - dB dB dB dB minimum setting; asymmetrical cut - - - Gstep(bass) FADER Gfader fader gain control see Table 84 maximum setting minimum setting - - step resolution gain (bass) see Table 80 0 -59 -80 - - -66 dB dB dB mute attenuation; 20 Hz to 20 kHz - input 2003 Oct 21 21 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H SYMBOL Gstep(fader) PARAMETER step resolution gain (fader) CONDITIONS see Table 84 Gfader = 0 to -15 dB Gfader = -15 to -45 dB Gfader = -45 to -51 dB Gfader = -51 to -59 dB MIN. - - - - 90 1 TYP. MAX. - - - - - UNIT dB dB dB dB dB 2.5 3 4 - mute audio mute volume control: mute and output muted (bits MULF, MURF, MULR and MURR) BEEP fbeep beep generator frequency see Table 93 BEF[1:0] = 00 BEF[1:0] = 01 BEF[1:0] = 10 BEF[1:0] = 11 Vbeep(rms) beep generator audio level (RMS value) see Table 92 BEL[2:0] = 000 BEL[2:0] = 001 BEL[2:0] = 010 BEL[2:0] = 011 BEL[2:0] = 100 BEL[2:0] = 101 BEL[2:0] = 110 BEL[2:0] = 111 THDbeep total harmonic distortion of beep generator fbeep = 1 kHz or 2 kHz - - - - - - - - - 0 13.3 18 28 44 60 90 150 - - - - - - - - - 7 mV mV mV mV mV mV mV mV % - - - - 500 1 2 3 - - - - Hz kHz kHz kHz Power-on reset (all registers in default setting, outputs muted, standby mode) Vth(POR) Notes 1. The LOW voltage of pin SCLG is influenced by VSCL: VSCLG(LOW) VSCL(LOW) + 0.22 V. 2. The equivalent level voltage is that value of the level voltage (at pin LEVEL) which results in the same weak signal control effect (for instance HCC roll-off) as the output value of the specified detector (USN, WAM and MPH). V bus(p-p) 3. Crosstalk between bus inputs and signal outputs: ct = 20log -------------------V o(rms) threshold voltage of Power-on reset - 6.3 - V 2003 Oct 21 22 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H handbook, full pagewidth V 18 14 10 6 MHC330 o (dB) 2 -2 -6 -10 -14 -18 10 +1.85 -1.90 102 103 104 faudio (Hz) 105 Gbass = +12 and -12 dB. Gtreble = +12 and -12 dB. fcut-off(treble) = 10 kHz. fc(bass) = 60 Hz. Fig.3 Equalizer bowing. 2003 Oct 21 23 Philips Semiconductors Product specification Car radio integrated signal processor 11 I2C-BUS PROTOCOL Table 1 S(1) Notes 1. S = START condition. 2. A = acknowledge. 3. P = STOP condition. Table 2 S(1) Notes 1. S = START condition. 2. A = acknowledge. 3. NA = not acknowledge. 4. P = STOP condition. Table 3 IC address byte IC ADDRESS 0 Table 4 BIT 7 to 2 1 0 11.1 11.1.1 Table 5 Read mode DATA BYTE 1; STATUS Format of data byte 1 BIT 6 ASIA BIT 5 AFUS BIT 4 POR BIT 3 RDAV BIT 2 ID2 BIT 1 ID1 0 1 1 0 0 ADDR Read mode address (read) A(2) data byte(s) A(2) data byte Write mode address (write) A(2) subaddress A(2) data byte(s) TEF6892H A(2) P(3) NA(3) P(4) MODE R/W Description of IC address byte SYMBOL - ADDR R/W 001100+(ADDR) = IC address. Address bit. 0 = pin ADDR is grounded; 1 = pin ADDR is floating. Read/Write. 0 = write mode; 1 = read mode. DESCRIPTION BIT 7 STIN BIT 0 ID0 2003 Oct 21 24 Philips Semiconductors Product specification Car radio integrated signal processor Table 6 BIT 7 6 5 Description of data byte 1 SYMBOL STIN ASIA AFUS DESCRIPTION TEF6892H Stereo indicator. 0 = no pilot signal detected; 1 = pilot signal detected. ASI active. 0 = not active; 1 = ASI step is in progress. AF update sample. 0 = LEV, USN and WAM information is taken from main frequency (continuous mode); 1 = LEV, USN and WAM information is taken from alternative frequency. Continuous mode during AF update and sampled mode after AF update. Sampled mode reverts to continuous main frequency information after read. Power-on reset. 0 = standard operation (valid I2C-bus register settings); 1 = Power-on reset detected since last read cycle (I2C-bus register reset). After read the bit will reset to POR = 0. RDS data available. This bit indicates, that RDS block data is available. Identification. TEF6892H device type identification; ID[2:0] = 010. 4 POR 3 2 to 0 11.1.2 Table 7 RDAV ID[2:0] DATA BYTE 2; LEVEL Format of data byte 2 BIT 6 LEV6 BIT 5 LEV5 BIT 4 LEV4 BIT 3 LEV3 BIT 2 LEV2 BIT 1 LEV1 BIT 0 LEV0 BIT 7 LEV7 Table 8 BIT 7 to 0 Description of data byte 2 SYMBOL LEV[7:0] DESCRIPTION Level. 8-bit value of level voltage from tuner; see Fig.4. handbook, halfpage 5 MHC331 Veq (V) 4 LEV [7:0] 255 3 2 1 0 0 0 1 2 3 4 5 VLEVEL (V) Fig.4 Equivalent level voltage Veq (MPH and LEV detector) as a function of level voltage VLEVEL. 2003 Oct 21 25 Philips Semiconductors Product specification Car radio integrated signal processor 11.1.3 Table 9 DATA BYTE 3; USN AND WAM Format of data byte 3 BIT 6 USN2 BIT 5 USN1 BIT 4 USN0 BIT 3 WAM3 BIT 2 WAM2 BIT 1 TEF6892H BIT 7 USN3 BIT 0 WAM0 WAM1 Table 10 Description of data byte 3 BIT 7 to 4 3 to 0 11.1.4 SYMBOL USN[3:0] WAM[3:0] DESCRIPTION Ultrasonic noise detector. USN content of the MPXRDS audio signal; see Fig.5. Wideband AM detector. WAM content of the LEVEL voltage; see Fig.6. DATA BYTE 4; RDS STATUS Table 11 Format of data byte 4 BIT 7 SYNC BIT 6 DOFL BIT 5 RSTD BIT 4 LBI2 BIT 3 LBI1 BIT 2 LBI0 BIT 1 ELB1 BIT 0 ELB0 Table 12 Description of data byte 4 BIT 7 6 5 4 to 2 1 and 0 11.1.5 SYMBOL SYNC DOFL RSTD LBI[2:0] ELB[1:0] DESCRIPTION Synchronization found status. 0 = synchronization is searched. 1 = synchronization found. Data overflow flag. 0 = normal operation. 1 = data overflow is detected (no update). Reset detected. 0 = normal operation. 1 = decoder reset (POR) is in progress. Last block identification. See Table 25. Error status last block. See Table 26. DATA BYTE 5; RDS LDATM Table 13 Format of data byte 5 BIT 7 LM15 BIT 6 LM14 BIT 5 LM13 BIT 4 LM12 BIT 3 LM11 BIT 2 LM10 BIT 1 LM9 BIT 0 LM8 Table 14 Description of data byte 5 BIT 7 to 0 11.1.6 SYMBOL LM[15:8] DESCRIPTION Block data of previously received RDS block, most significant byte. DATA BYTE 6; RDS LDATL Table 15 Format of data byte 6 BIT 7 LM7 BIT 6 LM6 BIT 5 LM5 BIT 4 LM4 BIT 3 LM3 BIT 2 LM2 BIT 1 LM1 BIT 0 LM0 Table 16 Description of data byte 6 BIT 7 to 0 2003 Oct 21 SYMBOL LM[7:0] DESCRIPTION Block data of previously received RDS block, least significant byte. 26 Philips Semiconductors Product specification Car radio integrated signal processor 11.1.7 DATA BYTE 7; RDS PDATM TEF6892H Table 17 Format of data byte 7 BIT 7 PM15 BIT 6 PM14 BIT 5 PM13 BIT 4 PM12 BIT 3 PM11 BIT 2 PM10 BIT 1 PM9 BIT 0 PM8 Table 18 Description of data byte 7 BIT 7 to 0 SYMBOL PM[15:8] DESCRIPTION Block data of previously received RDS block, most significant byte. Only relevant when reduced data request mode is active (DAC = 10; see Table 40). 11.1.8 DATA BYTE 8; RDS PDATL Table 19 Format of data byte 8 BIT 7 PM7 BIT 6 PM6 BIT 5 PM5 BIT 4 PM4 BIT 3 PM3 BIT 2 PM2 BIT 1 PM1 BIT 0 PM0 Table 20 Description of data byte 8 BIT 7 to 0 SYMBOL PM[7:0] DESCRIPTION Block data of previously received RDS block, least significant byte. Only relevant when reduced data request mode is active (DAC = 10; see Table 40). 11.1.9 DATA BYTE 9; RDS COUNT Table 21 Format of data byte 9 BIT 7 BBC5 BIT 6 BBC4 BIT 5 BBC3 BIT 4 BBC2 BIT 3 BBC1 BIT 2 BBC0 BIT 1 GBC5 BIT 0 GBC4 Table 22 Description of data byte 9 BIT 7 to 2 1 and 0 SYMBOL BBC[5:0] GBC[5:4] DESCRIPTION Bad block counter. Counter value of received invalid blocks; n = 0 to 63. Good block counter. Two most significant bits of received valid blocks counter; n = 0 to 62. Remark: the least significant bit is not available for reading (assume GBC0 = 0). 11.1.10 DATA BYTE 10; RDS PBIN Table 23 Format of data byte 10 BIT 7 GBC3 BIT 6 GBC2 BIT 5 GBC1 BIT 4 PBI2 BIT 3 PBI1 BIT 2 PBI0 BIT 1 EPB1 BIT 0 EPB0 2003 Oct 21 27 Philips Semiconductors Product specification Car radio integrated signal processor Table 24 Description of data byte 10 BIT 7 to 5 SYMBOL GBC[3:1] DESCRIPTION TEF6892H Good block counter. Three least significant bits of received valid blocks counter; n = 0 to 62. Remark: the least significant bit is not available for reading (assume GBC0 = 0). Previous block identification. See Table 25. Error status previous block. See Table 26. 4 to 2 1 and 0 PBI[2:0] EPB[1:0] Table 25 Description of data bits LBI[2:0] and PBI[2:0] LBI2 PBI2 0 0 0 0 1 1 1 1 LBI1 PBI1 0 0 1 1 0 0 1 1 LBI0 PBI0 0 1 0 1 0 1 0 1 BLOCK TYPE IDENTIFICATION OF LAST AND PREVIOUS RECEIVED BLOCK DATA A B C D C' E (RBDS mode) invalid E (RDS mode) invalid block Table 26 Description of data bits ELB[1:0] and EPB[1:0] ELB1 EPB1 0 0 1 1 11.2 Write mode ELB0 ERROR STATUS OF LAST AND PREVIOUS RECEIVED BLOCK DATA EPB0 0 1 0 1 no errors corrected burst error of maximum 2 bits corrected burst error of maximum 5 bits uncorrectable error Table 27 Format for subaddress byte with default setting BIT 7 AIOF - BIT 6 GATE 0 BIT 5 SGAT 0 BIT 4 SA4 - BIT 3 SA3 - BIT 2 SA2 - BIT 1 SA1 - BIT 0 SA0 - 2003 Oct 21 28 Philips Semiconductors Product specification Car radio integrated signal processor Table 28 Description of subaddress byte BIT 7 6 5 4 to 0 SYMBOL AIOF GATE SGAT SA[4:0] DESCRIPTION TEF6892H Auto-increment off. 0 = auto-increment enabled; 1 = auto-increment disabled. Gate. 0 = I2C-bus outputs (SDAG and SCLG) are controllable by the shortgate or the autogate function; 1 = I2C-bus outputs are enabled. Shortgate. 1 = I2C-bus outputs (SDAG and SCLG) are enabled for a single transmission following this control and disabled automatically. Data byte select. The subaddress value is auto-incremented when AIOF = 0 and will revert from SA = 30 to SA = 0. SA = 31 can only be accessed via direct subaddress selection, in which case auto-increment will revert from SA = 31 to SA = 0; see Table 29. Table 29 Selection of data byte SA4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 11.2.1 SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 1F MNEMONIC RDS SET A RDS SET B RDSCLK RDS CONTROL CONTROL CSALIGN MULTIPATH SNC HIGHCUT SOFTMUTE RADIO INPUT/ASI LOUDNESS VOLUME TREBLE BASS FADER BALANCE MIX BEEP AUTOGATE ADDRESSED DATA BYTE settings of RDS/RBDS settings of RDS/RBDS clock of RDS/RBDS control of RDS/RBDS function control of supply and AF update alignment of stereo channel separation control of weak signal sensitivity and timing alignment of SNC start and slope alignment of HCC start and slope alignment soft mute start and slope control of radio functions source selector and ASI settings loudness control volume control treble control bass control fader control balance control control of output mixer beep generator settings autogate control SUBADDRESS 0H; RDS SET A Table 30 Format of data byte 0H with default setting BIT 7 - 0 BIT 6 SYM1 0 BIT 5 SYM0 0 BIT 4 GBL5 1 BIT 3 GBL4 0 BIT 2 GBL3 0 BIT 1 GBL2 0 BIT 0 GBL1 1 2003 Oct 21 29 Philips Semiconductors Product specification Car radio integrated signal processor Table 31 Description of data byte 0H BIT 7 6 and 5 4 to 0 SYMBOL - SYM[1:0] GBL[5:1] Not used. Set to logic 0. Synchronization mode. See Table 32. DESCRIPTION TEF6892H Maximum good blocks lose (0 to 63). Number of valid blocks (good blocks counter) at which both the good block counter and the bad block counter are reset to 0. Only used when synchronized. GBL0 is located in byte RDS SET B. When the bad block counter reaches value BBL (see byte RDS SET B) before the good block counter reaches value GBL a new synchronization is started. Table 32 Description of synchronization mode SYM1 0 0 1 1 SYM0 0 1 0 1 SYNCHRONIZATION MODE no error correction; only error free blocks are handled as valid limited error correction; up to 2 bits error correctable blocks are handled as valid full error correction; up to 5 bits error correctable blocks are handled as valid mixed mode; only error free blocks are handled as valid for synchronization search, but when synchronized, up to 5 bits error correctable blocks are handled as valid 11.2.2 SUBADDRESS 1H; RDS SET B Table 33 Format of data byte 1H with default setting BIT 7 GBL0 0 BIT 6 RBDS 0 BIT 5 BBL5 0 BIT 4 BBL4 0 BIT 3 BBL3 0 BIT 2 BBL2 0 BIT 1 BBL1 0 BIT 0 BBL0 1 Table 34 Description of data byte 1H BIT 7 6 5 to 0 SYMBOL GBL0 RBDS BBL[5:0] DESCRIPTION Maximum good blocks lose (0 to 63); see Table 31. RBDS mode. 0 = RDS mode, RBDS type E blocks are handled as invalid (bad block); 1 = RBDS mode, RBDS type E blocks are handled as valid (good block). Maximum bad blocks lose (0 to 63). Number of invalid blocks (bad blocks counter) at which a new synchronization is started. Both the good block counter and the bad block counter are reset to 0. 11.2.3 SUBADDRESS 2H; RDSCLK Table 35 Format of data byte 2H with default setting BIT 7 - - BIT 6 - - BIT 5 TST3 0 BIT 4 TST2 0 BIT 3 TST1 0 BIT 2 TST0 0 BIT 1 CLKO 0 BIT 0 CLKI 1 2003 Oct 21 30 Philips Semiconductors Product specification Car radio integrated signal processor Table 36 Description of data byte 2H BIT 7 and 6 5 to 2 1 0 SYMBOL - TST[3:0] CLKO CLKI Not used. Set to logic 0. Test. TST[3:0] = 0000: normal operation. DESCRIPTION TEF6892H Clock input or output and buffered or unbuffered raw RDS output. See Table 37. Table 37 RDS clock description CLKO 0 0 1 1 11.2.4 CLKI 0 1 0 1 RDS/RBDS CLOCK RDS decoder mode; pin RDCL is disabled for RDS decoder bypass mode; RDCL is burst clock input for raw RDS read-out for RDS decoder mode: continuous block rate data available signal at pin RDCL; for RDS decoder bypass mode: RDCL is clock output for raw RDS read-out reserved SUBADDRESS 3H; RDS CONTROL Table 38 Format of data byte 3H with default setting BIT 7 DAC1 0 BIT 6 DAC0 0 BIT 5 NWSY 0 BIT 4 BBG4 0 BIT 3 BBG3 0 BIT 2 BBG2 0 BIT 1 BBG1 0 BIT 0 BBG0 0 Table 39 Description of data byte 3H BIT 7 and 6 5 SYMBOL DAC[1:0] NWSY DESCRIPTION Data available control. See Table 40. New synchronization search. 0 = synchronization is started by BBL value of bad block counter only; 1 = restart of synchronization search. NWSY is automatically reset to logic 0. Maximum bad blocks gain. Number of invalid blocks (bad block counter) that is allowed during synchronization search. If reached, a new synchronization is started. BBG[4:0] = 0 disables this function. 4 to 0 BBG[4:0] Table 40 Description of data available control DAC1 0 0 1 1 DAC0 0 1 0 1 DATA AVAILABLE CONTROL standard output mode; new block data is signalled at every new received block fast PI search mode; during synchronization search (SYNC = 0) A or C' block data is available and signalled, when synchronized standard output mode is active reduced data request mode; when synchronized new block data is signalled every two new received blocks decoder bypass mode; raw RDS data from demodulator is available on pin RDDA 2003 Oct 21 31 Philips Semiconductors Product specification Car radio integrated signal processor 11.2.5 SUBADDRESS 4H; CONTROL TEF6892H Table 41 Format of data byte 4H with default setting BIT 7 STBR 1 BIT 6 STBA 1 BIT 5 AFUM 0 BIT 4 AFUH 0 BIT 3 RMUT 0 BIT 2 - - BIT 1 LETF 0 BIT 0 ATTB 0 Table 42 Description of data byte 4H BIT 7 6 5 4 SYMBOL STBR STBA AFUM AFUH DESCRIPTION Standby mode RDS processing. 0 = RDS processing active; 1 = RDS processing in standby mode (RDS off, RDS outputs LOW). Standby mode audio processing. 0 = audio processing active; 1 = audio processing in standby mode (audio inputs and outputs at DC). Enables AF update mute. 0 = AF update mute disabled; 1 = AF update mute enabled (controlled by AFSAMP and AFHOLD input). AF update hold function. 0 = disable, the weak signal processing hold is controlled by the AFHOLD input only; 1 = hold. This is equal to taking the AFHOLD input LOW. The bit is reset to 0, when AFHOLD input is set to LOW (i.e. at AF update or preset change). Radio signal mute. 0 = no mute; 1 = mute with 1 ms ASI slope at start and stop. Not used. Set to logic 0. Fast level detector time constants. 0 = slow level detector time constants are used; 1 = fast level detector time constants are used. See Table 49. Attack bound of the MPH and LEV detector. 0 = detectors are unbounded; 1 = range of the MPH and LEV detector are limited in their range for immediate start of attack. In AM mode the detectors are always unbounded. 3 2 1 0 RMUT - LETF ATTB 11.2.6 SUBADDRESS 5H; CSALIGN Table 43 Format of data byte 5H with default setting BIT 7 CSR1 0 BIT 6 CSR0 1 BIT 5 CSA3 0 BIT 4 CSA2 1 BIT 3 CSA1 1 BIT 2 CSA0 1 BIT 1 - - BIT 0 - - Table 44 Description of data byte 5H BIT 7 and 6 5 to 2 1 and 0 SYMBOL CSR[1:0] CSA[3:0] - DESCRIPTION FM stereo channel separation (high frequency). See Table 45. FM stereo channel separation and adjustment. See Table 46. Not used. Set to logic 0. Table 45 FM stereo channel separation CSR1 0 0 1 1 2003 Oct 21 CSR0 0 1 0 1 32 FM STEREO CHANNEL SEPARATION (dB) 0 0.4 0.8 1.2 Philips Semiconductors Product specification Car radio integrated signal processor Table 46 FM stereo channel separation and adjustment CSA3 0 0 : 1 1 11.2.7 CSA2 0 0 : 1 1 CSA1 0 0 : 1 1 CSA0 0 1 : 0 1 TEF6892H FM STEREO CHANNEL SEPARATION AND ADJUSTMENT (dB) 0 0.2 : 2.8 3.0 SUBADDRESS 6H; MULTIPATH Table 47 Format of data byte 6H with default setting BIT 7 USS1 0 BIT 6 USS0 1 BIT 5 WAS1 0 BIT 4 WAS0 1 BIT 3 LET1 0 BIT 2 LET0 0 BIT 1 MPT1 0 BIT 0 MPT0 0 Table 48 Description of data byte 6H BIT 7 and 6 5 and 4 3 and 2 1 and 0 SYMBOL USS[1:0] WAS[1:0] LET[1:0] MPT[1:0] DESCRIPTION USN sensitivity for weak signal processing. See Fig.5. WAM sensitivity for weak signal processing. See Fig.6. LEVEL detector time constant. See Table 49. MPH detector time constants (level, WAM and USN). See Table 50. Table 49 Setting of the time constants of the LEVEL detector LETF 0 0 0 0 1 1 1 1 LET1 0 0 1 1 0 0 1 1 LET0 ATTACK 0 1 0 1 0 1 0 1 3 3 1.5 0.5 0.5 0.17 0.06 0.06 tLEVEL (s) DECAY 3 6 1.5 1.5 0.5 0.5 0.17 0.06 Table 50 Setting of the time constants of the MPH detector (level, WAM and USN) MPT1 0 0 1 1 2003 Oct 21 MPT0 ATTACK 0 1 0 1 33 0.5 0.5 0.5 0.25 tMPH (s) DECAY 12 24 6 6 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H handbook, halfpage 5 MHC332 Veq (V) handbook, halfpage 5 MHC333 Veq (V) 4 4 3 3 2 2 1 (1) (2) (3) (4) 1 (1) (2) (3) (4) 0 0 0.25 0.5 0.75 1 1.25 VMPXRDS(rms) (V) (1) (2) (3) (4) 0 0 0.2 0.4 0.6 0.8 1 VLEVEL(p-p) (V) (1) (2) (3) (4) USS[1:0] = 11 = -6 V/0.5 V. USS[1:0] = 10 = -4 V/0.5 V. USS[1:0] = 01 = -3 V/0.5 V. USS[1:0] = 00 = -2 V/0.5 V. WAS[1:0] = 11 = -6 V/0.4 V. WAS[1:0] = 10 = -4 V/0.4 V. WAS[1:0] = 01 = -3 V/0.4 V. WAS[1:0] = 00 = -2 V/0.4 V. Fig.5 Equivalent level voltage Veq (USN and MPH detector) as a function of MPX signal at 150 kHz. Fig.6 Equivalent level voltage Veq (WAM and MPH detector) as a function of level input at 21 kHz. 11.2.8 SUBADDRESS 7H; SNC Table 51 Format of data byte 7H with default setting BIT 7 SST3 0 BIT 6 SST2 1 BIT 5 SST1 1 BIT 4 SST0 1 BIT 3 SSL1 0 BIT 2 SSL0 1 BIT 1 HCMP 0 BIT 0 HCSF 0 Table 52 Description of data byte 7H BIT 7 to 4 3 and 2 1 0 SYMBOL SST[3:0] SSL[1:0] HCMP HCSF DESCRIPTION Start of the stereo blend SNC. See Table 53 and Fig.7. Slope of the stereo blend SNC. See Fig.8. High cut control source. 0 = control by the level (LEV) detector; 1 = control by the multipath (MPH) detector. High cut control minimum bandwidth. 0 = 2 kHz; 1 = 3 kHz. 2003 Oct 21 34 Philips Semiconductors Product specification Car radio integrated signal processor Table 53 Start of the stereo blend SNC SST3 SST2 SST1 SST0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 STEREO NOISE CONTROL START VOLTAGE (V) 1.88 1.94 2 2.06 2.13 2.19 2.25 2.31 SST3 SST2 SST1 SST0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TEF6892H STEREO NOISE CONTROL START VOLTAGE (V) 2.38 2.44 2.5 2.56 2.63 2.69 2.75 2.81 handbook, halfpage cs 50 MHC334 handbook, halfpage cs 50 MHC335 (dB) 40 (dB) 40 30 30 20 20 (1) (2) (3) (4) 10 (1) (2) (3) (4) 10 0 0.5 0 1 1.5 2 2.5 3 Veq (V) 1 1.5 2 2.5 Veq (V) 3 SSL[1:0] = 10 (1) SST[3:0] = 0000. (2) SST[3:0] = 0111. (3) SST[3:0] = 1000. (4) SST[3:0] = 1111. SST[3:0] = 1010 (1) SSL[1:0] = 00 = 38 dB/V. (2) SSL[1:0] = 01 = 51 dB/V. (3) SSL[1:0] = 10 = 63 dB/V. (4) SSL[1:0] = 11 = 72 dB/V. Fig.7 Channel separation cs as a function of equivalent level voltage Veq (start). Fig.8 Channel separation cs as a function of equivalent level voltage Veq (slope). 2003 Oct 21 35 Philips Semiconductors Product specification Car radio integrated signal processor 11.2.9 SUBADDRESS 8H; HIGHCUT TEF6892H Table 54 Format of data byte 8H with default setting BIT 7 HST2 0 BIT 6 HST1 1 BIT 5 HST0 1 BIT 4 HSL1 0 BIT 3 HSL0 1 BIT 2 HCF2 1 BIT 1 HCF1 1 BIT 0 HCF0 1 Table 55 Description of data byte 8H BIT 7 to 5 4 and 3 2 to 0 SYMBOL HST[2:0] HSL[1:0] HCF[2:0] DESCRIPTION High cut control start (weak signal processing). See Fig.9. High cut control slope (weak signal processing). See Fig.10. Fixed high cut control (maximum HCC bandwidth). See Table 56 and Fig.11. handbook, full pagewidth 0 MHC336 HCC (dB) 3 6 9 (1) (2) (3) (4) (5) (6) (7) (8) 12 15 0 0.5 1 1.5 2 2.5 3 Veq (V) 3.5 HCF[2:0] = 111, HCSF = 0, HSL[1:0] = 10 and faudio = 10 kHz (1) HST[2:0] = 000 = 1.5 V. (2) HST[2:0] = 001 = 1.75 V. (3) HST[2:0] = 010 = 2 V. (4) HST[2:0] = 011 = 2.25 V. (5) (6) (7) (8) HST[2:0] = 100 = 2.5 V. HST[2:0] = 101 = 3 V. HST[2:0] = 110 = 3.5 V. HST[2:0] = 111 = 4 V. Fig.9 High cut control attenuation HCC as a function of equivalent level voltage Veq (start). 2003 Oct 21 36 Philips Semiconductors Product specification Car radio integrated signal processor Table 56 Fixed high cut control handbook, halfpage TEF6892H HCC (dB) 0 MHC337 unlimited wide 10 6.8 HCF2 0 0 0 0 1 HCF1 0 0 1 1 0 0 1 1 HCF0 0 1 0 1 0 1 0 1 Bmax (kHz) 1.5 2.2 3.3 4.7 6.8 10 wide unlimited 3 Bmax (kHz) 6 (1) (2) 4.7 (3) (4) 3.3 9 HCSF = 1 12 HCSF = 0 15 1 1 1 2.2 1.5 18 0 0.5 1 1.5 2 2.5 Veq (V) HST[2:0] = 010 and faudio = 10 kHz (1) HSL[1:0] = 00 = 9 dB/V. (2) HSL[1:0] = 01 = 11 dB/V. (3) HSL[1:0] = 10 = 14 dB/V. (4) HSL[1:0] = 11 = 18 dB/V. Fig.10 High cut control attenuation HCC as a function of equivalent level voltage Veq (slope). GHCC handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 6 MHC338 f audio (Hz) Fig.11 High cut control gain GHCC as a function of audio frequency faudio (fixed HCC). 2003 Oct 21 37 Philips Semiconductors Product specification Car radio integrated signal processor 11.2.10 SUBADDRESS 9H; SOFTMUTE Table 57 Format of data byte 9H with default setting BIT 7 MST2 0 BIT 6 MST1 1 BIT 5 MST0 1 BIT 4 MSL1 0 BIT 3 MSL0 1 BIT 2 UMD1 0 BIT 1 UMD0 1 TEF6892H BIT 0 SMON 1 Table 58 Description of data byte 9H BIT 7 to 5 4 and 3 2 and 1 0 SYMBOL MST[2:0] MSL[1:0] UMD[1:0] SMON Soft mute slope. See Fig.13. USN mute depth. Maximum soft mute attenuation of the soft mute via USN control; see Fig.14. Soft mute enable. 0 = disable; 1 = enable. DESCRIPTION Soft mute start. mute = 3 dB; see Fig.12. handbook, halfpage mute (dB) 0 (2) (3) (4) (1) (5) (6) (7) MHC339 (8) handbook, halfpage 0 MHC340 mute (dB) 12 6 (1) (2) (3) 24 12 (4) 36 18 48 60 0.25 0.75 1.25 1.75 2.25 Veq (V) 24 0.25 0.5 0.75 1 1.25 1.5 Veq (V) MSL[1:0] = 11. (1) MST[2:0] = 000 = 0.75 V. (2) MST[2:0] = 001 = 0.88 V. (3) MST[2:0] = 010 = 1 V. (4) MST[2:0] = 011 = 1.12 V. MST[2:0] = 000. (5) (6) (7) (8) MST[2:0] = 100 = 1.25 V. MST[2:0] = 101 = 1.5 V. MST[2:0] = 110 = 1.75 V. MST[2:0] = 111 = 2 V. (1) MSL[1:0] = 00 = 8 dB/V. (2) MSL[1:0] = 01 = 16 dB/V. (3) MSL[1:0] = 10 = 24 dB/V. (4) MSL[1:0] = 11 = 32 dB/V. Fig.12 Soft mute attenuation mute as a function of equivalent level voltage Veq (start). Fig.13 Soft mute attenuation mute as a function of equivalent level voltage Veq (slope). 2003 Oct 21 38 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H handbook, halfpage 0 MHC341 mute (dB) (1) (2) (3) (4) a b 6 12 18 a. MST[2:0] = 000, MSL[1:0] = 11 b. MST[2:0] = 100, MSL[1:0] = 01 (1) UMD[1:0] = 00 = 3 dB. (2) UMD[1:0] = 01 = 6 dB. (3) UMD[1:0] = 10 = 9 dB. (4) UMD[1:0] = 11 = 12 dB. 24 0.25 0.5 0.75 1 1.25 1.5 Veq (V) Fig.14 Soft mute depth mute caused by ultrasonic noise. 11.2.11 SUBADDRESS AH; RADIO Table 59 Format of data byte AH with default setting BIT 7 AM 0 BIT 6 MONO 0 BIT 5 DEMP 1 BIT 4 ING1 0 BIT 3 ING0 0 BIT 2 SEAR 1 BIT 1 NBS1 1 BIT 0 NBS0 0 Table 60 Description of data byte AH BIT 7 6 5 4 and 3 2 1 and 0 SYMBOL AM MONO DEMP ING[1:0] SEAR NBS[1:0] DESCRIPTION AM selection. 0 = FM mode selected; 1 = AM mode selected. Stereo decoder mono. 0 = set to FM stereo; 1 = set to FM mono. De-emphasis time constant. 0 = 75 s; 1 = 50 s; see Fig.15. Input gain. See Table 61. LEVEL and MPH detector time constant. 0 = standard time constant selected; 1 = fast time constant of 60 ms selected. AM noise blanker and the FM noise blanker MPX sensitivity. See Table 62. 2003 Oct 21 39 Philips Semiconductors Product specification Car radio integrated signal processor Table 61 Input gain ING1 0 0 1 1 ING0 0 1 0 1 GAIN FOR FMMPX INPUT (dB) 0 3 6 23.5 GAIN FOR AM AND MPXRDS INPUT (dB) 0 3 6 0 0 0 1 1 0 1 0 1 Table 62 Noise blanker sensitivity SENSITIVITY OF FM NOISE BLANKER AT MPXRDS INPUT (mV) 90 150 210 270 TEF6892H NBS1 NBS0 SENSITIVITY OF AM NOISE BLANKER (%) 110 140 175 220 Gde-em handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 (1) 6 MHC342 (2) faudio (Hz) (1) de-em = 50 s. (2) de-em = 75 s. Fig.15 De-emphasis gain Gde-em as a function of audio frequency faudio. 2003 Oct 21 40 Philips Semiconductors Product specification Car radio integrated signal processor 11.2.12 SUBADDRESS BH; INPUT AND ASI Table 63 Format of data byte BH with default setting BIT 7 NBL1 1 BIT 6 NBL0 0 BIT 5 INP1 0 BIT 4 INP0 0 BIT 3 MUTE 1 BIT 2 ASI 1 BIT 1 AST1 0 TEF6892H BIT 0 AST0 0 Table 64 Description of data byte BH BIT 7 and 6 5 and 4 3 2 1 and 0 SYMBOL NBL[1:0] INP[1:0] MUTE ASI AST[1:0] DESCRIPTION FM noise blanker level sensitivity. See Table 65. Audio input tone/volume part. See Table 66. Audio mute. 0 = no mute; 1 = mute. Audio step interpolation. 0 = disable; 1 = enable. Audio step interpolation time constant. ASI time is 0 s when ASI = 0; see Table 67. Table 65 FM noise blanker level sensitivity NBL1 0 0 1 1 NBL0 0 1 0 1 SENSITIVITY OF FM NOISE BLANKER AT LEVEL INPUT (mV) 9 18 28 reserved Table 66 Audio input tone/volume part INP1 0 0 1 1 INP0 0 1 0 1 AUDIO INPUT FOR TONE/VOLUME PART radio CD tape phone Table 67 Audio step interpolation time constant AST1 0 0 1 1 11.2.13 SUBADDRESS CH; LOUDNESS Table 68 Format of data byte CH with default setting BIT 7 - - BIT 6 LDN4 0 BIT 5 LDN3 0 BIT 4 LDN2 0 BIT 3 LDN1 0 BIT 2 LDN0 0 BIT 1 LLF 1 BIT 0 LHB 1 AST0 0 1 0 1 ASI TIME (ms) 1 3 10 30 2003 Oct 21 41 Philips Semiconductors Product specification Car radio integrated signal processor Table 69 Description of data byte CH, see Figs 16 to 19 BIT 7 6 to 2 1 0 SYMBOL - LDN[4:0] LLF LHB Not used. Set to logic 0. Loudness gain. See Table 70. Loudness low boost frequency. 0 = 50 Hz; 1 = 100 Hz. DESCRIPTION TEF6892H Loudness high boost enable. 0 = loudness low boost is enabled; 1 = loudness low boost and loudness high boost are enabled. Table 70 Loudness gain LDN4 0 0 0 : 1 1 1 LDN3 0 0 0 : 0 0 0 LDN2 0 0 0 : 0 0 1 LDN1 0 0 1 : 1 1 0 LDN0 0 1 0 : 0 1 0 LOUDNESS CONTROL (dB) 0 -1 -2 : -18 -19 -20 Gloudness handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 6 MHC343 f audio (Hz) Fig.16 Loudness gain Gloudness as a function of audio frequency faudio; low boost frequency 50 Hz and high boost on. 2003 Oct 21 42 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H Gloudness handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 6 MHC344 f audio (Hz) Fig.17 Loudness gain Gloudness as a function of audio frequency faudio; low boost frequency 50 Hz and high boost off. Gloudness handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 6 MHC345 f audio (Hz) Fig.18 Loudness gain Gloudness as a function of audio frequency faudio; low boost frequency 100 Hz and high boost on. 2003 Oct 21 43 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H Gloudness handbook, full pagewidth (dB) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 10 102 103 104 105 6 MHC346 f audio (Hz) Fig.19 Loudness gain Gloudness as a function of audio frequency faudio; low boost frequency 100 Hz and high boost off. 11.2.14 SUBADDRESS DH; VOLUME Table 71 Format of data byte DH with default setting BIT 7 - - BIT 6 VOL6 0 BIT 5 VOL5 1 BIT 4 VOL4 0 BIT 3 VOL3 0 BIT 2 VOL2 0 BIT 1 VOL1 0 BIT 0 VOL0 0 Table 72 Description of data byte DH BIT 7 6 to 0 SYMBOL - VOL[6:0] Not used. Set to logic 0. Volume setting. See Table 73. DESCRIPTION Table 73 Volume setting VOL6 0 0 0 : 0 0 0 2003 Oct 21 VOL5 0 0 0 : 0 0 1 VOL4 0 0 0 : 1 1 0 VOL3 1 1 1 : 1 1 0 44 VOL2 1 1 1 : 1 1 0 VOL1 0 0 1 : 1 1 0 VOL0 0 1 0 : 0 1 0 GAIN (dB) 20 19 18 : 2 1 0 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H VOL6 0 0 : 1 1 1 VOL5 1 1 : 0 0 0 VOL4 0 0 : 1 1 1 VOL3 0 0 : 1 1 1 VOL2 0 0 : 0 0 1 VOL1 0 1 : 1 1 0 VOL0 1 0 : 0 1 0 GAIN (dB) -1 -2 : -58 -59 mute 11.2.15 SUBADDRESS EH; TREBLE Table 74 Format of data byte EH with default setting BIT 7 - - BIT 6 TRE2 0 BIT 5 TRE1 0 BIT 4 TRE0 0 BIT 3 TREM 1 BIT 2 TRF1 0 BIT 1 TRF0 1 BIT 0 - - Table 75 Description of data byte EH, see Fig.20 BIT 7 6 to 4 3 2 and 1 0 Table 76 Treble gain TRE2 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 TRE1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 TRE0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 TREM 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TREBLE CONTROL (dB) 14 12 10 8 6 4 2 0 0 -2 -4 -6 -8 -10 -12 -14 SYMBOL - TRE[2:0] TREM TRF[1:0] - Not used. Set to logic 0. Treble gain. See Table 76. Treble attenuation or gain. 0 = attenuation; 1 = gain; see Table 76. Treble frequency. See Table 77. Not used. Set to logic 0. DESCRIPTION 2003 Oct 21 45 Philips Semiconductors Product specification Car radio integrated signal processor Table 77 Treble frequency TRF1 0 0 1 1 TRF0 0 1 0 1 TREBLE FREQUENCY (kHz) 8 10 12 15 TEF6892H handbook, full pagewidth G 20 treble (dB) 15 MHC347 10 5 0 -5 -10 -15 -20 10 102 103 104 f audio (Hz) 105 Fig.20 Treble gain Gtreble as a function of audio frequency faudio, ftreble = 10 kHz. 11.2.16 SUBADDRESS FH; BASS Table 78 Format of data byte FH with default setting BIT 7 - - BIT 6 BAS2 0 BIT 5 BAS1 0 BIT 4 BAS0 0 BIT 3 BASM 1 BIT 2 BAF1 1 BIT 1 BAF0 0 BIT 0 BASH 0 Table 79 Description of data byte FH, see Figs 21 and 22 BIT 7 6 to 4 3 2 and 1 0 SYMBOL - BAS[2:0] BASM BAF[1:0] BASH Not used. Set to logic 0. Bass gain. See Table 80. Bass attenuation or gain. 0 = attenuation; 1 = gain; see Table 80. Bass frequency. See Table 81. Bass frequency response. 0 = band-pass; 1 = shelve curve (only guaranteed for BASM = 0). DESCRIPTION 2003 Oct 21 46 Philips Semiconductors Product specification Car radio integrated signal processor TEF6892H handbook, full pagewidth G 18 bass (dB) 14 10 6 MHC348 2 -2 -6 -10 -14 -18 10 102 103 104 f audio (Hz) 105 Fig.21 Bass gain Gbass as a function of audio frequency faudio; bass frequency 60 Hz, band-pass boost and shelve cut. handbook, full pagewidth G 18 bass (dB) 14 10 6 MHC349 2 -2 -6 -10 -14 -18 10 102 103 104 f audio (Hz) 105 Fig.22 Bass gain Gbass as a function of audio frequency faudio; bass frequency 60 Hz, band-pass boost and band-pass cut. 2003 Oct 21 47 Philips Semiconductors Product specification Car radio integrated signal processor Table 80 Bass gain BAS2 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Table 81 Bass frequency BAF1 0 0 1 1 BAF0 0 1 0 1 BASS FREQUENCY (Hz) 60 80 100 120 BAS1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 BAS0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 BASM 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TEF6892H BASS CONTROL (dB) 14 12 10 8 6 4 2 0 0 -2 -4 -6 -8 -10 -12 -14 11.2.17 SUBADDRESS 10H; FADER Table 82 Format of data byte 10H with default setting BIT 7 - - BIT 6 - - BIT 5 FAD4 0 BIT 4 FAD3 0 BIT 3 FAD2 0 BIT 2 FAD1 0 BIT 1 FAD0 0 BIT 0 FADM 1 Table 83 Description of data byte 10H BIT 7 and 6 5 to 1 0 SYMBOL - FAD[4:0] FADM Not used. Set to logic 0. Fader gain. See Table 84. Fader gain mode. 0 = front output attenuated; 1 = rear output attenuated. DESCRIPTION 2003 Oct 21 48 Philips Semiconductors Product specification Car radio integrated signal processor Table 84 Fader gain FAD4 0 0 0 : 0 0 1 1 : 1 1 1 1 1 1 FAD3 0 0 0 : 1 1 0 0 : 1 1 1 1 1 1 FAD2 0 0 0 : 1 1 0 0 : 0 0 1 1 1 1 FAD1 0 0 1 : 1 1 0 0 : 1 1 0 0 1 1 FAD0 0 1 0 : 0 1 0 1 : 0 1 0 1 0 1 TEF6892H FADER CONTROL (dB) 0 -1 -2 : -14 -15 -17.5 -20 : -42.5 -45 -48 -51 -55 -59 11.2.18 SUBADDRESS 11H; BALANCE Table 85 Format of data byte 11H with default setting BIT 7 BAL6 0 BIT 6 BAL5 0 BIT 5 BAL4 0 BIT 4 BAL3 0 BIT 3 BAL2 0 BIT 2 BAL1 0 BIT 1 BAL0 0 BIT 0 BALM 1 Table 86 Description of data byte 11H BIT 7 to 1 0 SYMBOL BAL[6:0] BALM Balance gain. See Table 87. Balance gain mode. 0 = left channel attenuated; 1 = right channel attenuated. DESCRIPTION Table 87 Balance gain BAL6 0 0 0 : 1 1 1 1 BAL5 0 0 0 : 0 0 0 0 BAL4 0 0 0 : 0 0 0 1 BAL3 0 0 0 : 1 1 1 0 BAL2 0 0 0 : 1 1 1 0 BAL1 0 0 1 : 0 1 1 0 BAL0 0 1 0 : 1 0 1 0 BALANCE CONTROL (dB) 0 -1 -2 : -77 -78 -79 mute 2003 Oct 21 49 Philips Semiconductors Product specification Car radio integrated signal processor 11.2.19 SUBADDRESS 12H; MIX Table 88 Format of data byte 12H with default setting BIT 7 MILF 0 BIT 6 MIRF 0 BIT 5 MILR 0 BIT 4 MIRR 0 BIT 3 MULF 1 BIT 2 MURF 1 BIT 1 MULR 1 TEF6892H BIT 0 MURR 1 Table 89 Description of data byte 12H BIT 7 6 5 4 3 2 1 0 SYMBOL MILF MIRF MILR MIRR MULF MURF MULR MURR DESCRIPTION Mixer left front LFOUT. 0 = no mix; 1 = mix with NAV input and BEEP. Mixer right front RFOUT. 0 = no mix; 1 = mix with NAV input and BEEP. Mixer left rear LROUT. 0 = no mix; 1 = mix with NAV input and BEEP. Mixer right rear RROUT. 0 = no mix; 1 = mix with NAV input and BEEP. Mutes left front LFOUT. 0 = no mute; 1 = mute except for NAV input and BEEP. Mutes right front RFOUT. 0 = no mute; 1 = mute except for NAV input and BEEP. Mutes left rear LROUT. 0 = no mute; 1 = mute except for NAV input and BEEP. Mutes right rear RROUT. 0 = no mute; 1 = mute except for NAV input and BEEP. 11.2.20 SUBADDRESS 13H; BEEP Table 90 Format of data byte 13H with default setting BIT 7 BEL2 0 BIT 6 BEL1 0 BIT 5 BEL0 0 BIT 4 BEF1 0 BIT 3 BEF0 0 BIT 2 NAV 0 BIT 1 - - BIT 0 - - Table 91 Description of data byte 13H BIT 7 to 5 4 and 3 2 1 and 0 Table 92 Beep level BEL2 0 0 0 0 1 1 1 1 BEL1 0 0 1 1 0 0 1 1 BEL0 0 1 0 1 0 1 0 1 BEEP LEVEL (mV) mute 13 18 28 44 60 90 150 SYMBOL BEL[2:0] BEF[1:0] NAV - Beep level. See Table 92. Beep frequency. See Table 93. Mute NAV. 0 = mute; 1 = no mute. Not used. Set to logic 0. DESCRIPTION 2003 Oct 21 50 Philips Semiconductors Product specification Car radio integrated signal processor Table 93 Beep frequency BEF1 0 0 1 1 11.2.21 SUBADDRESS 1FH; AUTOGATE Table 94 Format of data byte 1FH with default setting BIT 7 AGA6 - BIT 6 AGA5 - BIT 5 AGA4 - BIT 4 AGA3 - BIT 3 AGA2 - BIT 2 AGA1 - BIT 1 AGA0 - BEF0 0 1 0 1 TEF6892H BEEP FREQUENCY (Hz) 500 1000 2000 3000 BIT 0 AGOF 1 Table 95 Description of data byte 1FH BIT 7 to 1 SYMBOL AGA[6:0] DESCRIPTION I2C-bus device address definition. These bits define the I2C-bus device address definition for the automatic control of the I2C-bus loop through gate. The subaddress auto-increment function reverts from SA = 30 to SA = 0, excluding the AUTOGATE byte (SA = 31). The AUTOGATE byte can only be accessed via direct subaddress selection of SA = 31, in which case auto-increment will revert to SA = 0. Autogate function enable. 0 = enable; 1 = disable [The autogate function is not compatible with the TEA684x tuner devices. For the TEA684x the use of the shortgate (SGAT) function is advised]. 0 AGOF 2003 Oct 21 51 Philips Semiconductors Product specification Car radio integrated signal processor 12 TEST AND APPLICATION INFORMATION TEF6892H handbook, full pagewidth 220 nF 22 220 nF 20 220 nF 21 220 nF 24 220 nF 23 220 nF 25 220 nF 32 26 27 10 F LFOUT 10 F 28 10 F 29 10 F 30 RROUT LROUT RFOUT CDL CDR CDCM TAPEL TAPER PHONE PHCM JP11 JP12 100 nF NAV V2 (5 V) TEF6892H 16 VCC 22 nF 47 F 4.7 F JP13 10 k 10 10 k 22 nF V1 (8.5 V) AGND 1 k FMMPX 2.2 nF JP4 JP5 100 nF AM 10 nF MPXRDS 6 7 220 nF 5 17 18 41 44 AGND CREF DGND ADDR JP3 JP1 JP2 SCL SDA LEVEL SDAG 1 43 SCL 42 SCLG DGND AFSAMP AFHOLD FREF 3 4 10 9 11 39 38 37 2 JP6 JP7 JP8 JP9 10 k JP10 10 k coaxial connector (SMC) test pin and STOCKO connector jumper MHC355 SDA DGND RDCL RDDA RDQ RDSGND Fig.23 Test circuit. 2003 Oct 21 52 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Oct 21 CDL CDR CDCM TAPEL TAPER PHONE PHCM MPXRDS Philips Semiconductors Car radio integrated signal processor 7x 220 nF input select 22 20 21 24 23 25 26 + + - + + - + + INPUT + SELECT 0 to -20 dB low f: 50/100 Hz high boost vol: +20 to -59 dB bal: L/R, 0 to -79 dB mute +14 to -14 dB f: 8 to 15 kHz +14 to -14 dB f: 60 to 120 Hz shelve/band-pass front/rear 0 to -59 dB mute: LF, RF, LR, RR mix: LF, RF, LR, RR 27 LOUDNESS asi VOLUME/ BALANCE/ MUTE asi amfmsoftmute afumute TREBLE BASS asi FRONT/ REAR FADER asi 28 MUTE asi level/off pitch BEEP on/off 32 100 nF MIX 29 30 LFOUT RFOUT LROUT RROUT AUDIO STEP INTERPOLATION (asi) NAV asi time asi active roll-off correction 220 nF 5 MPX PILOT CANCEL 19 kHz level 100 nF AM fref 7 PILOT/ REFERENCE PLL stereo adjust fm/am f: 1.5 to 15 kHz/wide 50/75 s STEREO DECODER 38 kHz fmsnc stereo 57 kHz Iref NOISE BLANKER HIGH CUT DE-EMPHASIS 16 17 AGND 22 nF 47 F VCC amnb fmnb amfmhcc standby SUPPLY Vref 18 CREF 41 DGND addr I2C-BUS INTERFACE read 44 43 42 4.7 F NOISE DETECT nb sensitivity NOISE DETECT detection timings and control PULSE TIMER handbook, full pagewidth 53 amnb NICE 10 nF 6 USN TEF6892H ADDR SCL SDA DETECT 1 LEVEL DETECT SCL SDA 3 4 sclg sdag WAM DETECT level PULSE TIMER fmnb write autogate snc start, slope hcc start, slope sm start, slope sclg SNC HCC SM fmsnc amfmhcc amfmsoftmute sdag usn usn sensitivity wam wam sensitivity MULTIPATH/ WEAK SIGNAL DETECTION AND LOGIC reset/hold AFSAMP AFHOLD FREF 11 fref 8, 12, 13, 14, 15, 19, 31, 33, 34, 35, 36, 40 i.c. 10 9 hold afus afumute RDS mode 57 kHz RDS DEMODULATOR rds 39 RDCL RDDA 38 37 RDS DECODER Product specification TEF6892H RDQ 2 RDSGND MHC357 Fig.24 Application diagram. Philips Semiconductors Product specification Car radio integrated signal processor 13 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm TEF6892H SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-08-01 03-02-25 2003 Oct 21 54 Philips Semiconductors Product specification Car radio integrated signal processor 14 SOLDERING 14.1 Introduction to soldering surface mount packages TEF6892H To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Oct 21 55 Philips Semiconductors Product specification Car radio integrated signal processor 14.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP(8) Notes not suitable not suitable(4) TEF6892H SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable suitable not not recommended(5)(6) recommended(7) not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages. 2003 Oct 21 56 Philips Semiconductors Product specification Car radio integrated signal processor 15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION TEF6892H This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Oct 21 57 Philips Semiconductors Product specification Car radio integrated signal processor 18 PURCHASE OF PHILIPS I2C COMPONENTS TEF6892H Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Oct 21 58 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/01/pp59 Date of release: 2003 Oct 21 Document order number: 9397 750 10355 |
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